Temperature measurement circuits are well known in the art. Typical implementations take advantage of the properties of a bipolar transistor (BJT). As is well known, the base emitter voltage of such a transistor (in the case of a NPN type transistor or the emitter base voltage of the PNP equivalent) may be given to a first order approximation by the equationVbe=[k*T/q]ln(Ic/Is)  Equation 1where k=Boltzmann's constant, T=absolute temperature, q=electronic charge, Ic=collector current, Is=device saturation current.
One commonly used technique to generate a PTAT (proportional to absolute temperature) voltage is to take the difference of two Vbe's (δVbe). A number of different implementations can be used and these allow for various trade-offs to be made. Two general circuits are shown in FIG. 1. In part A of FIG. 1, the circuit is static and does not require any switching signals, whereas part B of FIG. 1 is a dynamic circuit, i.e., uses a switched current technique.
The method of FIG. 1, part A, uses identical devices operating at a different current or scaled BJT areas and uses the same current in each (see FIG. 1a). IfVeb1=[k*T/q]ln(I1/A1*Is)  Equation 2andVeb2=[k*T/q]ln(I2/A2*Is)  Equation 3then the difference in base emitter voltages between the two devices is given by:δVbe=Veb2−Veb1=Vptat Vptat=[k*T/q]ln[(I2*A1)/(I1*A2)  Equation 4
From an examination of δVbe, as defined in Equation 4, it will be seen that it is made up from two main components. The first component kT/q is a fixed value independent of the process whereas the second term ln[(I2*A1)/(11*A2), includes two possible sources of error. One of these can be linked to process variations in the manufacture of the two transistor devices with the resultant variations that can be introduced into the scaled value of A1/A2. The second source of error can be linked to errors associated with the current sources. The effect of both of these problems may be reduced somewhat by increasing device area at the expense of chip size.
The circuit of part B of FIG. 1 obviates the problems associated with the scaled areas of the two devices by using a single device and switching the currents into the device. The signal is generated over at least two clock phases: i.e., ph1-->Ie—q3=I3, ph2-->Ie—q3=I4 and then a comparison of the emitter voltages in both phases is effected to generate the PTAT signal. M1–M4 are the switches used to switch the currents in the various phases.δVbe=Vptat=[k*T/q]ln[I4/I3]  Equation 5
Such a technique is disclosed in U.S. Pat. No. 5,982,221 which is commonly assigned to the assignee of the present invention, the disclosure of which is incorporated herein by reference. As will be appreciated from a review of this disclosure, the PTAT voltage of this implementation can be doubled by using the additional output from Q4, if desired. It will be apparent that this technique is only affected by the ratios of the two currents. By increasing the operating current levels it is possible to improve the current ratio matching, but such increases introduce problems in circuits adapted for temperature measurements in that self-heating effects are introduced. Other techniques that could be used to minimize the effect of the current matching include trimming or calibration of the circuit.
(a) Trimming:
This would typically be performed at either wafer probe or final test stage. A disadvantage of trimming is that it is typically performed at a single temperature. If the current matching changes with temperature, then this will limit the accuracy achievable. Furthermore, some form of non-volatile memory is also required which introduces additional cost, and complexity. Another factor to consider is that trimming techniques require sufficient trim resolution to achieve the required precision, which is necessary for accurate temperature measurement circuits.
(b) Calibration:
Calibration routines are typically implemented by the user, after the device is powered up. Usually, an iterative algorithm is used to calibrate out any error sources i.e., matching errors. Again, additional memory would be required to store the calibration coefficients, and a suitable calibration algorithm would need to be developed. This added complexity could make the device less attractive to the user as it may require frequent re-calibration.
A temperature to digital converter that uses a sensor based on the principle of switching accurately scaled currents is described in IEEE Journal of Solid State Circuits, Vol. 33, No. 7, July 1998 by Mike Tuthill. In this circuit, which is implemented in a CMOS process, a plurality (18) of current sources are provided which are ratioed in a 17:1 configuration. For each of four different switching phases a different PMOS device is selected, thereby averaging the error in the current-source ratio. To achieve this switching of the four individual devices in and out, each of the four devices are provided in the center of a current source array, surrounded by the remainder.
U.S. Pat. No. 5,990,725 describes another technique that strives to provide an accurate ratio between the two currents used to generate the PTAT voltage without requiring the techniques of trimming or calibration. This specification describes a temperature measurement with an interleaved bi-level current on a diode and bi-level current source therefore which claims to provide an accurate ratio of the measurement currents through the diode without calibration and despite process variations. The circuitry uses a plurality (x) of individual current sources wherein the higher current of the ratio is provided by the sum of the x currents and the lower current by a selected one of the x current sources. In effect, if a first current source is labelled I(1) or I1 and there are x current sources provided, then the sum of the current sources is       ∑          j      =      1        x    ⁢          ⁢      I    ⁡          (      j      )      and the ratio at a first instance is given by       [                  ∑                  j          =          1                x            ⁢                          ⁢              I        ⁡                  (          j          )                      ]    /      I1    .  The temperature measurement is made using x higher current/lower current measuring sequences and using a different one of the x individual current sources for each sequence. It further describes how by proper ordering of the sequence used, that an output temperature may be provided which is representative of the temperature of the diode at the beginning of the x sequences, at the end of the x measurement sequence or half way between the two. A problem associated with this technique is that the values of the current across the transistor/diode for I1 and for       ∑          j      =      1        x    ⁢          ⁢      I    ⁡          (      j      )      are of one another. This requires the current sources to be switched on and off, which can introduce temperature variations into the chip. There therefore still exists a need to provide for an improved circuit and method that can provide an accurate source of the current ratio.
A further problem with temperature measurement circuits is the need to calibrate or test the circuitry. Typically, this is achieved by monitoring the signal output from the device under test (DUT) and comparing it with the output from other known devices such as resistive temperature devices (RTD) co-located within the test environment with the DUT. By assuming that the RTD and the DUT device are both monitoring the same temperature, one can generate a comparison between the outputs of the individual devices. Such assumptions are not always accurate as there can be temperature gradients within the test environment and as such the RTD and DUT devices are not in effect measuring the same value. There is therefore a need to provide for a circuit and technique that can provide for a better indication of the actual temperature sensed by the device under test.